Table of Contents
Foreword
| FOREWORD |
PDF
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| Koichiro ISHIBASHI | 467-467 |
| FOREWORD |
PDF
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| Eisuke TOKUMITSU | 639-639 |
Letters
| Power Optimization of an 8051-Compliant IP Microcontroller |
PDF
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| Luca FANUCCI, Sergio SAPONARA, Alexander MORELLO | 597-600 |
| An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications |
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| Jang-Jin NAM, Hong-June PARK | 773-777 |
Papers
| A 1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks |
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| Jun TERADA, Yasuyuki MATSUYA, Shin'ichiro MUTOH, Yuichi KADO | 479-483 |
| Sub-1-V Power-Supply System with Variable-Stage SC-Type DC-DC Converter Scheme for Ambient Energy Sources |
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| Yoshifumi YOSHIDA, Fumiyasu UTSUNOMIYA, Takakuni DOUSEKI | 484-489 |
| A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters |
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| Toru TANZAWA, Kenichi AGAWA, Hiroyuki SHIBAYAMA, Ryota TERAUCHI, Katsumi HISANO, Hiroki ISHIKURO, Shouhei KOUSAI, Hiroyuki KOBAYASHI, Hideaki MAJIMA, Toru TAKAYAMA, Masayuki KOIZUMI, Fumitoshi HATORI | 490-495 |
| CMOS Radio Design for Complete Single Chip GPS SoC |
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| Norihito SUZUKI, Takahide KADOYAMA, Masayuki KATAKURA | 496-501 |
| A 300-MHz-Band, Sub-1 V and Sub-1 mW CMOS SAW Oscillator Suitable for Use in RF Transmitters |
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| Minoru KOZAKI, Norio HAMA | 502-508 |
| Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor |
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| Takahiro SEKI, Satoshi AKUI, Katsunori SENO, Masakatsu NAKAI, Tetsumasa MEGURO, Tetsuo KONDO, Akihiko HASHIGUCHI, Hirokazu KAWAHARA, Kazuo KUMANO, Masayuki SHIMURA | 520-527 |
| A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones |
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| Makoto ISHIKAWA, Tatsuya KAMEI, Yuki KONDO, Masanao YAMAOKA, Yasuhisa SHIMAZAKI, Motokazu OZAWA, Saneaki TAMAKI, Mikio FURUYAMA, Tadashi HOSHI, Fumio ARAKAWA, Osamu NISHII, Kenji HIROSE, Shinichi YOSHIOKA, Toshihiro HATTORI | 528-535 |
| Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router |
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| Michitaka OKUNO, Shin-ichi ISHIDA, Hiroaki NISHI | 536-543 |
| An Energy-Efficient Clustered Superscalar Processor |
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| Toshinori SATO, Akihiro CHIYONOBU | 544-551 |
| A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era |
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| Kazutoshi KOBAYASHI, Masao ARAMOTO, Hidetoshi ONODERA | 552-558 |
| A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation |
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| Junichi MIYAKOSHI, Yuichiro MURACHI, Koji HAMANO, Tetsuro MATSUNO, Masayuki MIYAMA, Masahiko YOSHIMOTO | 559-569 |
| An Exact Leading Non-Zero Detector for a Floating-Point Unit |
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| Fumio ARAKAWA, Tomoichi HAYASHI, Masakazu NISHIBORI | 570-575 |
| Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm |
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| Shoichi MASUI, Kenji MUKAIDA, Masahiko TAKENAKA, Naoya TORII | 576-581 |
| A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation |
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| Takakuni DOUSEKI, Toshishige SHIMAMURA, Nobutaro SHIBATA | 582-588 |
| Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits |
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| Kenji SHIMAZAKI, Makoto NAGATA, Takeshi OKUMOTO, Shozo HIRANO, Hiroyuki TSUJIKAWA | 589-596 |
| Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications |
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| Kouji TSUNODA, Akira SATO, Hiroko TASHIRO, Toshiro NAKANISHI, Hitoshi TANAKA | 608-613 |
| The Umbrella Cell: A High-Density 2T Cell for SOC Applications |
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| Satoru AKIYAMA, Takao WATANABE, Nobuhiro OODAIRA, Tsuyoshi ISHIKAWA, Digh HISAMOTO | 614-621 |
| Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh |
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| Hideyuki NODA, Kazunari INOUE, Hans Jurgen MATTAUSCH, Tetsushi KOIDE, Katsumi DOSAKA, Kazutami ARIMOTO, Kazuyasu FUJISHIMA, Kenji ANAMI, Tsutomu YOSHIHARA | 622-629 |
| 0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier |
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| Toshikazu SUZUKI, Yoshinobu YAMAGAMI, Ichiro HATANAKA, Akinori SHIBAYAMA, Hironori AKAMATSU, Hiroyuki YAMAUCHI | 630-638 |
| Electrical Characterization of Aluminum-Oxynitride Stacked Gate Dielectrics Prepared by a Layer-by-Layer Process of Chemical Vapor Deposition and Rapid Thermal Nitridation |
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| Hideki MURAKAMI, Wataru MIZUBAYASHI, Hirokazu YOKOI, Atsushi SUYAMA, Seiichi MIYAZAKI | 640-645 |
| Characterization of Atom Diffusion in Polycrystalline Si/SiGe/Si Stacked Gate |
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| Hideki MURAKAMI, Yoshikazu MORIWAKI, Masafumi FUJITAKE, Daisuke AZUMA, Seiichiro HIGASHI, Seiichi MIYAZAKI | 646-650 |
| Thermally Robust Nickel Silicide Process for Nano-Scale CMOS Technology |
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| Soon-Young OH, Jang-Gn YUN, Bin-Feng HUANG, Yong-Jin KIM, Hee-Hwan JI, Sang-Bum HUH, Han-Seob CHA, Ui-Sik KIM, Jin-Suk WANG, Hi-Deok LEE | 651-655 |
| Separation by Bonding Si Islands (SBSI) for Advanced CMOS LSI Applications |
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| Takashi YAMAZAKI, Shun-ichiro OHMI, Shinya MORITA, Hiroyuki OHRI, Junichi MUROTA, Masao SAKURABA, Hiroo OMI, Tetsushi SAKAI | 656-661 |
| Effects of Electric Field on Metal-Induced Lateral Crystallization under Limited Ni-Supply Condition |
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| Gou NAKAGAWA, Noritoshi SHIBATA, Tanemasa ASANO | 662-666 |
| Low Temperature Poly-Si Thin Film Transistor on Plastic Substrates |
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| Jang Yeon KWON, Do Young KIM, Hans S. CHO, Kyung Bae PARK, Ji Sim JUNG, Jong Man KIM, Young Soo PARK, Takashi NOGUCHI | 667-671 |
| Composite-Collector InGaP/GaAs HBTs for Linear Power Amplifiers |
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| Takaki NIWA, Takashi ISHIGAKI, Naoto KUROSAWA, Hidenori SHIMAWAKI, Shinichi TANAKA | 672-677 |
| Low Phase Noise, InGaP/GaAs HBT VCO MMIC for Millimeter-Wave Applications |
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| Satoshi KURACHI, Toshihiko YOSHIMASU | 678-682 |
| Evaluation of Surface States of AlGaN/GaN HFET Using Open-Gated Structure |
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| Daigo KIKUTA, Jin-Ping AO, Yasuo OHNO | 683-689 |
| Low On-Voltage Operation AlGaN/GaN Schottky Barrier Diode with a Dual Schottky Structure |
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| Seikoh YOSHIDA, Nariaki IKEDA, Jiang LI, Takahiro WADA, Hironari TAKEHARA | 690-693 |
| High Ruggedness Power MOSFET Design by a Self-Align p+ Process |
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| Feng-Tso CHIEN, Ming-Hung LAI, Shih-Tzung SU, Kou-Way TU, Ching-Ling CHENG | 694-698 |
| Novel 4RTD Logic Circuits |
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| Hideaki YAMADA, Takao WAHO | 699-704 |
| Characterization of Germanium Nanocrystallites Grown on SiO2 by a Conductive AFM Probe Technique |
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| Katsunori MAKIHARA, Yoshihiro OKAMOTO, Hideki MURAKAMI, Seiichiro HIGASHI, Seiichi MIYAZAKI | 705-708 |
| Charging and Discharging Characteristics of Stacked Floating Gates of Silicon Quantum Dots |
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| Taku SHIBAGUCHI, Mitsuhisa IKEDA, Hideki MURAKAMI, Seiichi MIYAZAKI | 709-712 |
| TE Plane Wave Reflection and Transmission from a One-Dimensional Random Slab |
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| Yasuhiko TAMURA, Junichi NAKAYAMA | 713-720 |
| Optimal Position of Isolator to Suppress Double Rayleigh Backscattering Noise in Fiber Raman Amplifiers |
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| Wenning JIANG, Jianping CHEN, Junhe ZHOU | 721-724 |
| A Temperature and Supply Independent Bias Circuit and MMIC Power Amplifier Implementation for W-CDMA Applications |
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| Youn Sub NOH, Jong Heung PARK, Chul Soon PARK | 725-728 |
| Harmonic-Injected Power Amplifier with 2nd Harmonic Short Circuit for Cellular Phones |
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| Shigeo KUSUNOKI, Tadanaga HATSUGAI | 729-738 |
| Application of the Eigen-Mode Expansion Method to Power/Ground Plane Structures with Holes |
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| Ping LIU, Zheng-Fan LI | 739-743 |
| Multicarrier Power Amplifier Linearization Based on Artificial Intelligent Methods |
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| Masoud FAROKHI, Mahmoud KAMAREI, S. Hamaidreza JAMALI | 744-752 |
| Design Techniques of Delay-Locked Loop for Jitter Minimization in DRAM Applications |
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| In-Young CHUNG, Youngsoo SOHN, Wonki PARK, Changhyun KIM | 753-759 |
| Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's |
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| Kyeong-Sik MIN, Kouichi KANDA, Hiroshi KAWAGUCHI, Kenichi INAGAKI, Fayez Robert SALIBA, Hoon-Dae CHOI, Hyun-Young CHOI, Daejeong KIM, Dong Myong KIM, Takayasu SAKURAI | 760-767 |
| An 8b 220 MS/s 0.25 µm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References |
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| Young-Jae CHO, Hyuen-Hee BAE, Seung-Hoon LEE | 768-772 |
Invited Papers
| Low-Power Design of High-Speed A/D Converters |
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| Shoji KAWAHITO, Kazutaka HONDA, Masanori FURUTA, Nobuhiro KAWAI, Daisuke MIYAZAKI | 468-478 |
| Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits |
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| Farzan FALLAH, Massoud PEDRAM | 509-519 |
| A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory |
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| Shoichi MASUI, Toshiyuki TERAMOTO | 601-607 |