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Table of Contents
Foreword
| FOREWORD |
PDF
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| Akira MATSUZAWA | 211-212 |
Letters
| Trends of On-Chip Interconnects in Deep Sub-Micron VLSI |
PDF
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| Danardono Dwi ANTONO, Kenichi INAGAKI, Hiroshi KAWAGUCHI, Takayasu SAKURAI | 392-394 |
| A New Approach to Mixed-Path Propagation of Surface Wave |
PDF
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| Bin-hao JIANG | 434-436 |
| Quantum Noise and Feed-Back Noise in Blue-Violet InGaN Semiconductor Lasers |
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| Kenjiro MATSUOKA, Kazushi SAEKI, Eiji TERAOKA, Minoru YAMADA, Yuji KUWAMURA | 437-439 |
| Low Power Low Phase Noise LC Quadrature VCO Topology |
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| Ji-Hoon KIM, Hyung-Joun YOO | 440-442 |
Papers
| VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation |
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| Noriyuki MINEGISHI, Junichi MIYAKOSHI, Yuki KURODA, Tadayoshi KATAGIRI, Yuki FUKUYAMA, Ryo YAMAMOTO, Masayuki MIYAMA, Kousuke IMAMURA, Hideo HASHIMOTO, Masahiko YOSHIMOTO | 230-242 |
| A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier |
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| Jumpei UCHIDA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI | 243-249 |
| Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits |
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| Nobuaki KOBAYASHI, Tomomi EI, Tadayoshi ENOMOTO | 271-279 |
| Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping |
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| Canh Quang TRAN, Hiroshi KAWAGUCHI, Takayasu SAKURAI | 280-286 |
| Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core |
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| Tetsuya YAMADA, Masahide ABE, Yusuke NITTA, Kenji OGURA, Manabu KUSAOKE, Makoto ISHIKAWA, Motokazu OZAWA, Kiwamu TAKADA, Fumio ARAKAWA, Osamu NISHII, Toshihiro HATTORI | 287-294 |
| A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology |
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| Chi-Nan CHUANG, Shen-Iuan LIU | 295-299 |
| Channel-Count-Independent BIST for Multi-Channel SerDes |
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| Kouichi YAMAGUCHI, Muneo FUKAISHI | 314-319 |
| A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology |
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| Daisuke MIZOGUCHI, Noriyuki MIURA, Takayasu SAKURAI, Tadahiro KURODA | 320-326 |
| Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect |
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| Yoichi YUYAMA, Akira TSUCHIYA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA | 327-333 |
| An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques |
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| Masahiro NOMURA, Taku OHSAWA, Koichi TAKEDA, Yoetsu NAKAZAWA, Yoshinori HIROTA, Yasuhiko HAGIHARA, Naoki NISHI | 334-341 |
| A Statistical Quality Model for Delay Testing |
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| Yasuo SATO, Shuji HAMADA, Toshiyuki MAEDA, Atsuo TAKATORI, Seiji KAJIHARA | 349-355 |
| Multi-Ported Register File for Reducing the Impact of PVT Variation |
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| Yuuichirou IKEDA, Masaya SUMITA, Makoto NAGATA | 356-363 |
| Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply |
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| Toru NAKURA, Makoto IKEDA, Kunihiro ASADA | 364-369 |
| On-Chip Detector for Single-Event Noise Sensing with Voltage Scaling Function |
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| Mohamed ABBAS, Makoto IKEDA, Kunihiro ASADA | 370-376 |
| Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment |
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| Makoto SUGIHARA, Taiga TAKATA, Kenta NAKAMURA, Ryoichi INANAMI, Hiroaki HAYASHI, Katsumi KISHIMOTO, Tetsuya HASEBE, Yukihiro KAWANO, Yusuke MATSUNAGA, Kazuaki MURAKAMI, Katsuya OKUMURA | 377-383 |
| Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond |
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| Yoshihide KOMATSU, Yukio ARIMA, Koichiro ISHIBASHI | 384-391 |
| Propagation Analysis of Circular Surface Waveguides with a Periodically Corrugated Ground Plane |
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| Chin-Jui LAI, Ching-Her LEE, Chung-I G. HSU, Jean-Fu KIANG | 395-402 |
| Aperture-Backed Microstrip-Line Stepped-Impedance Resonators and Transformers for Performance-Enhanced Bandpass Filters |
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| Hang WANG, Lei ZHU | 403-409 |
| Extraction of LRGC Matrices for 8-Coupled Uniform Lossy Transmission Lines Using 2-Port VNA Measurements |
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| Hyun Bae LEE, Kyoungho LEE, Hae Kang JUNG, Hong June PARK | 410-419 |
| A Fast Switching Low Phase Noise CMOS Frequency Synthesizer with a New Coarse Tuning Method for PHS Applications |
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| Kang-Yoon LEE, Hyunchul KU, Young Beom KIM | 420-428 |
| Evaluation of the Fusional Limit between the Front and Rear Images in Depth-Fused 3-D Visual Illusion |
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| Hideaki TAKADA, Shiro SUYAMA, Munekazu DATE | 429-433 |
Invited Papers
| System LSI: Challenges and Opportunities |
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| Tadahiro KURODA | 213-220 |
| Design Philosophy of a Networking-Oriented Data-Driven Processor: CUE |
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| Hiroaki NISHIKAWA | 221-229 |
| Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond |
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| Koichiro ISHIBASHI, Tetsuya FUJIMOTO, Takahiro YAMASHITA, Hiroyuki OKADA, Yukio ARIMA, Yasuyuki HASHIMOTO, Kohji SAKATA, Isao MINEMATSU, Yasuo ITOH, Haruki TODA, Motoi ICHIHASHI, Yoshihide KOMATSU, Masato HAGIWARA, Toshiro TSUKADA | 250-262 |
| Module-Wise Dynamic Voltage and Frequency Scaling for a 90 nm H.264/MPEG-4 Codec LSI |
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| Yukihito OOWAKI, Shinichiro SHIRATAKE, Toshihide FUJIYOSHI, Mototsugu HAMADA, Fumitoshi HATORI, Masami MURAKATA, Masafumi TAKAHASHI | 263-270 |
| Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies |
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| Hirotaka TAMURA, Masaya KIBUNE, Hisakatsu YAMAGUCHI, Kouichi KANDA, Kohtaroh GOTOH, Hideki ISHIDA, Junji OGAWA | 300-313 |
| Variability: Modeling and Its Impact on Design |
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| Hidetoshi ONODERA | 342-348 |