Table of Contents
Foreword
| FOREWORD |
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| Tsuneo TSUKAHARA | 663-663 |
Letters
| A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications |
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| Yasuhiro SUGIMOTO, Yuji GOHDA, Shigeto TANAKA | 811-813 |
| A Technique to Reduce Power Consumption for a Linear Transconductor |
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| Fujihiko MATSUMOTO, Isamu YAMAGUCHI, Akira YACHIDATE, Yasuaki NOGUCHI | 814-818 |
| Design of Analog Current-Mode Loser-Take-All Circuit |
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| Mohsen ASLONI, Abdollah KHOEI, Khayrollah HADIDI | 819-822 |
| Reduction of the Intensity Noise by Electric Positive and Negative Feedback in Blue-Violet InGaN Semiconductor Lasers |
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| Minoru YAMADA, Kazushi SAEKI, Eiji TERAOKA, Yuji KUWAMURA | 858-860 |
| Improvements in the Design of Matrix Distributed Amplifiers |
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| Emad HAMIDI, Mahmoud MOHAMMAD- TAHERI | 861-864 |
| Novel First-Order Non-inverting and Inverting Output of All-Pass Filter at the Same Configuration Using ICCII |
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| Hua-Pin CHEN, Ming-Tzau LIN, Wan-Shing YANG | 865-867 |
| A CMOS Built-In Current Sensor for IDDQ Testing |
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| Jeong Beom KIM, Seung Ho HONG | 868-870 |
Papers
| A Reduced-Sample-Rate Sigma-Delta-Pipeline ADC Architecture for High-Speed High-Resolution Applications |
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| Vahid MAJIDZADEH, Omid SHOAEI | 692-701 |
| Design of a Small-Offset 12-Bit CMOS DAC Using Weighted Mean Sample-and-Hold Circuit |
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| Masayuki UNO, Shoji KAWAHITO | 702-709 |
| Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits |
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| Zheng LIU, Masanori FURUTA, Shoji KAWAHITO | 710-716 |
| An Image Rejection Mixer with AI-Based Improved Performance for WCDMA Applications |
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| Yuji KASAI, Kiyoshi MIYASHITA, Hidenori SAKANASHI, Eiichi TAKAHASHI, Masaya IWATA, Masahiro MURAKAWA, Kiyoshi WATANABE, Yukihiro UEDA, Kaoru TAKASUKA, Tetsuya HIGUCHI | 717-724 |
| True 50% Duty-Cycle SSH and SHH SiGe BiCMOS Divide-by-3 Prescalers |
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| Sheng-Che TSENG, Chinchun MENG, Wei-Yu CHEN | 725-731 |
| Extended Phase Noise Performance in Mutual Negative Resistance CMOS LC Oscillator for Low Supply Voltages |
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| Apisak WORAPISHET | 732-738 |
| A -90 dBc@10 kHz Phase Noise Fractional-N Frequency Synthesizer with Accurate Loop Bandwidth Control Circuit |
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| Shiro DOSHO, Takashi MORIE, Koji OKAMOTO, Yuuji YAMADA, Kazuaki SOGAWA | 739-745 |
| A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector |
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| Ching-Yuan YANG, Yu LEE, Cheng-Hsing LEE | 746-752 |
| All-Digital Clock Deskew Buffer with Variable Duty Cycles |
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| Shao-Ku KAO, Shen-Iuan LIU | 753-760 |
| An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity |
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| Koichiro NOGUCHI, Makoto NAGATA | 761-768 |
| A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique |
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| Takeshi YOSHIDA, Yoshihiro MASUI, Takayuki MASHIMO, Mamoru SASAKI, Atsushi IWATA | 769-774 |
| Modified CMOS Op-Amp with Improved Gain and Bandwidth |
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| Mahdi MOTTAGHI- KASHTIBAN, Khayrollah HADIDI, Abdollah KHOEI | 775-780 |
| An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture |
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| Osamu NOMURA, Takashi MORIE, Keisuke KOREKADO, Teppei NAKANO, Masakazu MATSUGU, Atsushi IWATA | 781-791 |
| MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm |
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| Chia-Chi CHU, Ming-Hong LAI, Wu-Shiung FENG | 792-802 |
| A Method Using an Averaging Technique for the Analysis and Evaluation of Real Quasi-Resonant Converters |
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| Yi-Cherng LIN, Der-Cherng LIAW | 803-810 |
| Extended-Range High-Resolution FMCW Reflectometry by Means of Electronically Frequency-Multiplied Sampling Signal Generated from Auxiliary Interferometer |
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| Koichi IIYAMA, Makoto YASUDA, Saburo TAKAMIYA | 823-829 |
| Numerical Investigation of Octagonal Photonic Crystal Fibers with Strong Confinement Field |
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| Kenta KANESHIMA, Yoshinori NAMIHIRA, Nianyu ZOU, Hiroki HIGA, Yasunori NAGATA | 830-837 |
| A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era |
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| Kazutoshi KOBAYASHI, Akihiko HIGUCHI, Hidetoshi ONODERA | 838-843 |
| Low-Latency Superscalar and Small-Code-Size Microcontroller Core for Automotive, Industrial, and PC-Peripheral Applications |
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| Yasuo SUGURE, Seiji TAKEUCHI, Yuichi ABE, Hiromichi YAMADA, Kazuya HIRAYANAGI, Akihiko TOMITA, Kesami HAGIWARA, Takeshi KATAOKA, Takanori SHIMURA | 844-850 |
| A Spread-Spectrum Clock Generator Using Fractional-N PLL with an Extended Range ΣΔ Modulator |
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| Yi-Bin HSIEH, Yao-Huang KAO | 851-857 |
Invited Papers
| Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use |
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| Masao HOTTA, Tatsuji MATSUURA | 664-672 |
| Ultra-Low Voltage Analog Integrated Circuits |
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| Shouri CHATTERJEE, Yannis TSIVIDIS, Peter KINGET | 673-680 |
| RF Passive Components Using Metal Line on Si CMOS |
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| Kazuya MASU, Kenichi OKADA, Hiroyuki ITO | 681-691 |