Vol. E89-C, No. 11 November 2006

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Table of Contents

Foreword

FOREWORD PDF
Takahiro HANYU 1491-1491

Letters

A Low-Power Write Driver for Hard Disk Drives PDF
Tatsuya KAWASHIMO, Hiroki YAMASHITA, Masayoshi YAGYU, Fumio YUKI 1670-1673
A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications PDF
Yeong-Kang LAI, Lien-Fei CHEN, Jian-Chou CHEN, Chun-Wei CHIU 1674-1675
Wave Absorber Formed by Arranging Cylindrical Bars at Intervals for Installing between ETC Lanes PDF
Kouta MATSUMOTO, Takeru OZAWA, Takuya NAKAMURA, Takahiro AOYAGI, Osamu HASHIMOTO, Takashi MIYAMOTO 1700-1703
High Efficiency Open Collector Adaptive Bias SiGe HBT Differential Power Amplifier PDF
Kuei-Cheng LIN, Tsung-Yu YANG, Kuan-Yu CHEN, Hwann-Kaeo CHIOU 1704-1707
Mode Converter Optimization for U-Style Rotary Joint PDF
Dong-Hyun KIM, Jeong-Woo JWA, Doo-Yeong YANG 1708-1712
Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems PDF
Wenliang TSENG, Chien-Nan Jimmy LIU, Chauchin SU 1713-1718

Papers

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design PDF
Takayuki GYOHTEN, Fukashi MORISHITA, Isamu HAYASHI, Mako OKAMOTO, Hideyuki NODA, Katsumi DOSAKA, Kazutami ARIMOTO, Yasutaka HORIBA 1519-1525
A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation PDF
Hiroyuki YAMAUCHI, Toshikazu SUZUKI, Yoshinobu YAMAGAMI 1526-1534
An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs PDF
Kenji SHIMAZAKI, Makoto NAGATA, Mitsuya FUKAZAWA, Shingo MIYAHARA, Masaaki HIRATA, Kazuhiro SATOH, Hiroyuki TSUJIKAWA 1535-1543
Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond PDF
Noriaki ODA, Hiroyuki KUNISHIMA, Takashi KYOUNO, Kazuhiro TAKEDA, Tomoaki TANAKA, Toshiyuki TAKEWAKI, Masahiro IKEDA 1544-1550
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification PDF
Masanori HARIYAMA, Shigeo YAMADERA, Michitaka KAMEYAMA 1551-1558
Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise PDF
Mitsuya FUKAZAWA, Makoto NAGATA 1559-1566
High-Frequency Low-Noise Voltage-Controlled LC-Tank Oscillators Using a Tunable Inductor Technique PDF
Ching-Yuan YANG, Meng-Ting TSAI 1567-1574
Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic PDF
Naoya ONIZAWA, Takahiro HANYU 1575-1580
Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach PDF
Yohei FUKUMIZU, Makoto NAGATA, Kazuo TAKI 1581-1590
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic PDF
Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Takahiro HANYU 1591-1597
Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing PDF
Tomohiro TAKAHASHI, Takahiro HANYU 1598-1604
Vision Chip Architecture for Detecting Line of Sight Including Saccade PDF
Junichi AKITA, Hiroaki TAKAGI, Takeshi NAGASAKI, Masashi TODA, Toshio KAWASHIMA, Akio KITAGAWA 1605-1611
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC PDF
Hideyuki NODA, Katsumi DOSAKA, Hans Jurgen MATTAUSCH, Tetsushi KOIDE, Fukashi MORISHITA, Kazutami ARIMOTO 1612-1619
Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic PDF
Michitaka OKUNO, Shinji NISHIMURA, Shin-ichi ISHIDA, Hiroaki NISHI 1620-1628
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing PDF
Junichi MIYAKOSHI, Yuichiro MURACHI, Tomokazu ISHIHARA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO 1629-1636
A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory PDF
Kan'ya SASAKI, Takashi MORIE, Atsushi IWATA 1637-1644
Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic PDF
Naofumi HOMMA, Takafumi AOKI, Tatsuo HIGUCHI 1645-1654
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates PDF
Masanori HARIYAMA, Sho OGATA, Michitaka KAMEYAMA 1655-1661
CMOS Image Sensor Using Negative-Feedback Resetting to Obtain Variably Smoothed Images PDF
Masayuki IKEBE, Keita SAITO 1662-1669
Error Analysis of the Multilevel Fast Multipole Algorithm PDF
Shinichiro OHNUKI, Weng Cho CHEW 1676-1681
Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit ΣΔ Modulator-Controlled Fractional PLL PDF
Masaru KOKUBO, Takashi KAWAMOTO, Takashi OSHIMA, Takayuki NOTO, Masato SUZUKI, Shigeyuki SUZUKI, Takashi HAYASAKA, Tomoaki TAKAHASHI, Jun KASAI 1682-1688
Autonomous di/dt Control of Power Supply for Margin Aware Operation PDF
Toru NAKURA, Makoto IKEDA, Kunihiro ASADA 1689-1694
Calculation of Measurement Uncertainties of Synchronously Sampled AC Signals in Nonideal Synchronization with Fundamental Frequency PDF
Predrag PETROVIC 1695-1699

Invited Papers

Solid-Electrolyte Nanometer Switch PDF
Naoki BANNO, Toshitsugu SAKAMOTO, Noriyuki IGUCHI, Hisao KAWAURA, Shunichi KAERIYAMA, Masayuki MIZUNO, Kozuya TERABE, Tsuyoshi HASEGAWA, Masakazu AONO 1492-1498
Carbon Nanotube Technologies for LSI via Interconnects PDF
Yuji AWANO 1499-1503
Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions PDF
Yoshihito AMEMIYA 1504-1511
Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture PDF
Toru SHIMIZU, Masami NAKAJIMA, Masahiro KAINAGA 1512-1518