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Table of Contents
Foreword
| FOREWORD |
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| Takahiro HANYU | 1491-1491 |
Letters
| A Low-Power Write Driver for Hard Disk Drives |
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| Tatsuya KAWASHIMO, Hiroki YAMASHITA, Masayoshi YAGYU, Fumio YUKI | 1670-1673 |
| A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications |
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| Yeong-Kang LAI, Lien-Fei CHEN, Jian-Chou CHEN, Chun-Wei CHIU | 1674-1675 |
| Wave Absorber Formed by Arranging Cylindrical Bars at Intervals for Installing between ETC Lanes |
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| Kouta MATSUMOTO, Takeru OZAWA, Takuya NAKAMURA, Takahiro AOYAGI, Osamu HASHIMOTO, Takashi MIYAMOTO | 1700-1703 |
| High Efficiency Open Collector Adaptive Bias SiGe HBT Differential Power Amplifier |
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| Kuei-Cheng LIN, Tsung-Yu YANG, Kuan-Yu CHEN, Hwann-Kaeo CHIOU | 1704-1707 |
| Mode Converter Optimization for U-Style Rotary Joint |
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| Dong-Hyun KIM, Jeong-Woo JWA, Doo-Yeong YANG | 1708-1712 |
| Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems |
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| Wenliang TSENG, Chien-Nan Jimmy LIU, Chauchin SU | 1713-1718 |
Papers
| An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design |
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| Takayuki GYOHTEN, Fukashi MORISHITA, Isamu HAYASHI, Mako OKAMOTO, Hideyuki NODA, Katsumi DOSAKA, Kazutami ARIMOTO, Yasutaka HORIBA | 1519-1525 |
| A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (Vth) Variation |
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| Hiroyuki YAMAUCHI, Toshikazu SUZUKI, Yoshinobu YAMAGAMI | 1526-1534 |
| An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs |
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| Kenji SHIMAZAKI, Makoto NAGATA, Mitsuya FUKAZAWA, Shingo MIYAHARA, Masaaki HIRATA, Kazuhiro SATOH, Hiroyuki TSUJIKAWA | 1535-1543 |
| Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond |
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| Noriaki ODA, Hiroyuki KUNISHIMA, Takashi KYOUNO, Kazuhiro TAKEDA, Tomoaki TANAKA, Toshiyuki TAKEWAKI, Masahiro IKEDA | 1544-1550 |
| Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification |
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| Masanori HARIYAMA, Shigeo YAMADERA, Michitaka KAMEYAMA | 1551-1558 |
| Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise |
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| Mitsuya FUKAZAWA, Makoto NAGATA | 1559-1566 |
| High-Frequency Low-Noise Voltage-Controlled LC-Tank Oscillators Using a Tunable Inductor Technique |
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| Ching-Yuan YANG, Meng-Ting TSAI | 1567-1574 |
| Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic |
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| Naoya ONIZAWA, Takahiro HANYU | 1575-1580 |
| Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach |
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| Yohei FUKUMIZU, Makoto NAGATA, Kazuo TAKI | 1581-1590 |
| Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic |
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| Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Takahiro HANYU | 1591-1597 |
| Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing |
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| Tomohiro TAKAHASHI, Takahiro HANYU | 1598-1604 |
| Vision Chip Architecture for Detecting Line of Sight Including Saccade |
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| Junichi AKITA, Hiroaki TAKAGI, Takeshi NAGASAKI, Masashi TODA, Toshio KAWASHIMA, Akio KITAGAWA | 1605-1611 |
| A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC |
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| Hideyuki NODA, Katsumi DOSAKA, Hans Jurgen MATTAUSCH, Tetsushi KOIDE, Fukashi MORISHITA, Kazutami ARIMOTO | 1612-1619 |
| Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic |
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| Michitaka OKUNO, Shinji NISHIMURA, Shin-ichi ISHIDA, Hiroaki NISHI | 1620-1628 |
| A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing |
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| Junichi MIYAKOSHI, Yuichiro MURACHI, Tomokazu ISHIHARA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO | 1629-1636 |
| A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory |
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| Kan'ya SASAKI, Takashi MORIE, Atsushi IWATA | 1637-1644 |
| Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic |
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| Naofumi HOMMA, Takafumi AOKI, Tatsuo HIGUCHI | 1645-1654 |
| A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates |
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| Masanori HARIYAMA, Sho OGATA, Michitaka KAMEYAMA | 1655-1661 |
| CMOS Image Sensor Using Negative-Feedback Resetting to Obtain Variably Smoothed Images |
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| Masayuki IKEBE, Keita SAITO | 1662-1669 |
| Error Analysis of the Multilevel Fast Multipole Algorithm |
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| Shinichiro OHNUKI, Weng Cho CHEW | 1676-1681 |
| Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit ΣΔ Modulator-Controlled Fractional PLL |
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| Masaru KOKUBO, Takashi KAWAMOTO, Takashi OSHIMA, Takayuki NOTO, Masato SUZUKI, Shigeyuki SUZUKI, Takashi HAYASAKA, Tomoaki TAKAHASHI, Jun KASAI | 1682-1688 |
| Autonomous di/dt Control of Power Supply for Margin Aware Operation |
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| Toru NAKURA, Makoto IKEDA, Kunihiro ASADA | 1689-1694 |
| Calculation of Measurement Uncertainties of Synchronously Sampled AC Signals in Nonideal Synchronization with Fundamental Frequency |
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| Predrag PETROVIC | 1695-1699 |
Invited Papers
| Solid-Electrolyte Nanometer Switch |
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| Naoki BANNO, Toshitsugu SAKAMOTO, Noriyuki IGUCHI, Hisao KAWAURA, Shunichi KAERIYAMA, Masayuki MIZUNO, Kozuya TERABE, Tsuyoshi HASEGAWA, Masakazu AONO | 1492-1498 |
| Carbon Nanotube Technologies for LSI via Interconnects |
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| Yuji AWANO | 1499-1503 |
| Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions |
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| Yoshihito AMEMIYA | 1504-1511 |
| Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture |
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| Toru SHIMIZU, Masami NAKAJIMA, Masahiro KAINAGA | 1512-1518 |