Vol. E90-C, No. 4 April 2007

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Table of Contents

Foreword

FOREWORD PDF
Tadahiro KURODA 655-656

Letters

The Front-End LSI with a 5-Tap PRML for 2 Reading and Writing of BD-R/RW/ROM PDF
GoangSeog CHOI, JumHan BAE, HyunSoo PARK 727-730
A Novel Low-Power Bus Design for Bus-Invert Coding PDF
Myungchul YOON, Byeong-hee ROH 731-734
Low Grazing Scattering from Periodic Neumann Surface with Finite Extent PDF
Junichi NAKAYAMA, Kazuhiro HATTORI, Yasuhiko TAMURA 903-906
A Cost-Effective Transition between a Microstrip Line and a Post-Wall Waveguide Using a Laminated LTCC Substrate in 60-GHz Band PDF
Takafumi KAI, Jiro HIROKAWA, Makoto ANDO, Hiroshi NAKANO, Yasutake HIRACHI 907-910

Papers

Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation PDF
Masaaki IIJIMA, Masayuki KITAMURA, Masahiro NUMA, Akira TADA, Takashi IPPOSHI, Shigeto MAEGAWA 666-674
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations PDF
Masao MORIMOTO, Makoto NAGATA, Kazuo TAKI 675-682
Design and Evaluation of a 5454-bit Multiplier Based on Differential-Pair Circuitry PDF
Akira MOCHIZUKI, Hirokatsu SHIRAHAMA, Takahiro HANYU 683-691
Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias PDF
Yoshihide KOMATSU, Koichiro ISHIBASHI, Makoto NAGATA 692-698
A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations PDF
Kazuya KATSUKI, Manabu KOTANI, Kazutoshi KOBAYASHI, Hidetoshi ONODERA 699-707
Cooperative Cache System: A Low Power Cache System for Embedded Processors PDF
Gi-Ho PARK, Kil-Whan LEE, Tack-Don HAN, Shin-Dug KIM 708-717
A Multiple Block-matching Step (MBS) Algorithm for H.26x/MPEG4 Motion Estimation and a Low-Power CMOS Absolute Differential Accumulator Circuit PDF
Tadayoshi ENOMOTO, Nobuaki KOBAYASHI, Tomomi EI 718-726
A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's PDF
Fayez Robert SALIBA, Hiroshi KAWAGUCHI, Takayasu SAKURAI 743-748
A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses PDF
Hiroyuki YAMAUCHI, Toshikazu SUZUKI, Yoshinobu YAMAGAMI 749-757
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation PDF
Riichiro TAKEMURA, Kiyoo ITOH, Tomonori SEKIGUCHI, Satoru AKIYAMA, Satoru HANZAWA, Kazuhiko KAJIGAYA, Takayuki KAWAHARA 758-764
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI PDF
Fukashi MORISHITA, Hideyuki NODA, Isamu HAYASHI, Takayuki GYOHTEN, Mako OKAMOTO, Takashi IPPOSHI, Shigeto MAEGAWA, Katsumi DOSAKA, Kazutami ARIMOTO 765-771
Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories PDF
Kazuo OTSUGA, Hideaki KURATA, Satoshi NODA, Yoshitaka SASAGO, Tsuyoshi ARIGANE, Tetsufumi KAWAMURA, Takashi KOBAYASHI 772-778
An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors PDF
Koichi ISHIDA, Atit TAMTRAKARN, Hiroki ISHIKURO, Makoto TAKAMIYA, Takayasu SAKURAI 786-792
Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop PDF
Win CHAIVIPAS, Akira MATSUZAWA 793-801
A Multi-Band Burst-Mode Clock and Data Recovery Circuit PDF
Che-Fu LIANG, Sy-Chyuan HWU, Shen-Iuan LIU 802-810
18-GHz Clock Distribution Using a Coupled VCO Array PDF
Takayuki SHIBASAKI, Hirotaka TAMURA, Kouichi KANDA, Hisakatsu YAMAGUCHI, Junji OGAWA, Tadahiro KURODA 811-822
An Integrated Low-Power CMOS Up-Conversion Mixer Using New Stacked Marchand Baluns PDF
Ivan Chee Hong LAI, Minoru FUJISHIMA 823-828
Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link PDF
Kiichi NIITSU, Noriyuki MIURA, Mari INOUE, Yoshihiro NAKAGAWA, Masamoto TAGO, Masayuki MIZUNO, Takayasu SAKURAI, Tadahiro KURODA 829-835
Source/Drain Optimization of Double Gate FinFET Considering GIDL for Low Standby Power Devices PDF
Katsuhiko TANAKA, Kiyoshi TAKEUCHI, Masami HANE 842-847
Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation PDF
Noriaki ODA, Hironori IMURA, Naoyoshi KAWAHARA, Masayoshi TAGAMI, Hiroyuki KUNISHIMA, Shuji SONE, Sadayuki OHNISHI, Kenta YAMADA, Yumi KAKUHARA, Makoto SEKINE, Yoshihiro HAYASHI, Kazuyoshi UENO 848-855
All Optical Analog-to-Digital Conversion by Polarization Modulation Using Nonlinear Phase Shift PDF
Yoshitomo SHIRAMIZU, Nobuo GOTO 856-864
Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders PDF
Hiroaki SUZUKI, Woopyo JEONG, Kaushik ROY 865-876
A Current-Steering DAC Architecture with Novel Switching Scheme for GPON Burst-Mode Laser Drivers PDF
Wei CHEN, Johan BAUWELINCK, Peter OSSIEUR, Xing-Zhi QIU, Jan VANDEWEGE 877-884
Shot Noise Modeling in Metal-Oxide-Semiconductor Field Effect Transistors under Sub-Threshold Condition PDF
Yoshioki ISOBE, Kiyohito HARA, Dondee NAVARRO, Youichi TAKEDA, Tatsuya EZAKI, Mitiko MIURA- MATTAUSCH 885-894
A CMOS Temperature Sensor Circuit PDF
Takashi OHZONE, Tatsuaki SADAMOTO, Takayuki MORISHITA, Kiyotaka KOMOKU, Toshihiro MATSUDA, Hideyuki IWATA 895-902

Invited Papers

Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS PDF
Kazutami ARIMOTO, Toshihiro HATTORI, Hidehiro TAKATA, Atsushi HASEGAWA, Toru SHIMIZU 657-665
Low-Voltage Embedded RAMs in Nanometer Era PDF
Takayuki KAWAHARA 735-742
Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS PDF
Akira MATSUZAWA 779-785
Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations PDF
Toshiro HIRAMOTO, Toshiharu NAGUMO, Tetsu OHTOU, Kouki YOKOYAMA 836-841