Table of Contents
Foreword
| FOREWORD |
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| Michitaka KAMEYAMA | 1849-1849 |
Letters
VLSI Implementation of a 4 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic |
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| Yasuhiro TAKAHASHI, Toshikazu SEKINE, Michio YOKOYAMA | 2002-2006 |
| Preliminary Demonstration of 1.0 V CMOS Imager with Semi-Pixel-Level ADC Based on Pulse-Width-Modulation Pixel Readout |
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| Keiichiro KAGAWA, Makoto SHOUHO, Kazuo HASHIGUCHI, Masahiro NUNOSHITA, Jun OHTA | 2007-2011 |
| Comparing the Performance of MMIC Matrix and Distributed Amplifiers |
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| Emad HAMIDI, Mahmoud MOHAMMAD- TAHERI | 2057-2061 |
| Improvements in the Transient Response of Distributed Amplifiers |
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| Emad HAMIDI, Mahmoud MOHAMMAD- TAHERI | 2062-2066 |
Papers
| Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade |
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| Junichi AKITA, Hiroaki TAKAGI, Keisuke DOUMAE, Akio KITAGAWA, Masashi TODA, Takeshi NAGASAKI, Toshio KAWASHIMA | 1869-1875 |
| An Image-Moment Sensor with Variable-Length Pipeline Structure |
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| Atsushi IWASHITA, Takashi KOMURO, Masatoshi ISHIKAWA | 1876-1883 |
| Wide View Imaging System Using Eight Random Access Image Sensors |
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| Kenji IDE, Ryusuke KAWAHARA, Satoshi SHIMIZU, Takayuki HAMAMOTO | 1884-1891 |
| Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI |
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| Satoshi SHIGEMATSU, Hiroki MORIMURA, Toshishige SHIMAMURA, Takahiro HATANO, Namiko IKEDA, Yukio OKAZAKI, Katsuyuki MACHIDA, Mamoru NAKANISHI | 1892-1899 |
| A Power Modeling and Optimization Scheme for Future Ultra Small Size Electric Systems |
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| Masahiro FUKUI, Sayaka IWAKOSHI, Tatsuya KOYAGI | 1900-1908 |
| Variant X-Tree Clock Distribution Network and Its Performance Evaluations |
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| Xu ZHANG, Xiaohong JIANG, Susumu HORIGUCHI | 1909-1918 |
A 90 nm 48 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations |
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| Kazutoshi KOBAYASHI, Kazuya KATSUKI, Manabu KOTANI, Yuuri SUGIHARA, Yohei KUME, Hidetoshi ONODERA | 1919-1926 |
| A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform |
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| Hiroki SHIMANO, Fukashi MORISHITA, Katsumi DOSAKA, Kazutami ARIMOTO | 1927-1935 |
| MRAM Applications Using Unlimited Write Endurance |
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| Tadahiko SUGIBAYASHI, Takeshi HONDA, Noboru SAKIMURA, Shuichi TAHARA, Naoki KASAI | 1936-1940 |
| A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip |
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| Shoichiro KAWASHIMA, Isao FUKUSHI, Keizo MORITA, Ken-ichi NAKABAYASHI, Mitsuharu NAKAZAWA, Kazuaki YAMANE, Tomohisa HIRAYAMA, Toru ENDO | 1941-1948 |
| Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes |
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| Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Yusuke IGUCHI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO | 1949-1956 |
| A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications |
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| Hidehiro TOYODA, Shinji NISHIMURA, Michitaka OKUNO, Matsuaki TERADA | 1957-1963 |
| Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms |
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| Qi WANG, Kazunori SHIMIZU, Takeshi IKENAGA, Satoshi GOTO | 1964-1971 |
| A Next-Generation Enterprise Server System with Advanced Cache Coherence Chips |
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| Mariko SAKAMOTO, Akira KATSUNO, Go SUGIZAKI, Toshio YOSHIDA, Aiichiro INOUE, Koji INOUE, Kazuaki MURAKAMI | 1972-1982 |
| Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems |
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| Makoto SUGIHARA, Tohru ISHIHARA, Kazuaki MURAKAMI | 1983-1991 |
| CPU Model-Based Mechatronics/Hardware/Software Co-design Technology for Real-Time Embedded Control Systems |
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| Makoto ISHIKAWA, George SAIKALIS, Shigeru OHO | 1992-2001 |
| Cascaded Lithium Niobate Mach-Zehnder Optical SSB Modulators for Multi-Carrier Signals |
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| Koji KIKUSHIMA, Toshihito FUJIWARA | 2012-2021 |
| A Miniaturized In-Phase Power Divider with a DC Block Function |
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| Hitoshi HAYASHI, Tadao NAKAGAWA, Kazuhiro UEHARA, Yoshihiro TAKIGAWA | 2022-2029 |
| Wide-Band Coaxial-to-Coplanar Transition |
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| Toshihisa KAMEI, Yozo UTSUMI, Nguyen Quoc DINH, Nguyen THANH | 2030-2036 |
| A 10 b 200 MS/s 1.8 mm2 83 mW 0.13 µm CMOS ADC Based on Highly Linear Integrated Capacitors |
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| Young-Ju KIM, Young-Jae CHO, Doo-Hwan SA, Seung-Hoon LEE | 2037-2043 |
| An Ultra Low-Voltage Ultra Low-Power CMOS Threshold Voltage Reference |
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| Luis H.C. FERREIRA, Tales C. PIMENTA, Robson L. MORENO | 2044-2050 |
| Parasitic Effects in Multi-Gate MOSFETs |
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| Yusuke KOBAYASHI, C. Raghunathan MANOJ, Kazuo TSUTSUI, Venkanarayan HARIHARAN, Kuniyuki KAKUSHIMA, V. Ramgopal RAO, Parhat AHMET, Hiroshi IWAI | 2051-2056 |
Invited Papers
| Media Processing LSI Architectures for Automotives -- Challenges and Future Trends -- |
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| Ichiro KURODA, Shorin KYO | 1850-1857 |
| CMOS Imaging Devices for New Markets of Vision Systems |
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| Shoji KAWAHITO | 1858-1868 |
4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic