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Table of Contents
Foreword
| FOREWORD |
PDF
|
| Masao NAKAYA | 399-399 |
Letters
| An Ultra-Low-Voltage Ultra-Low-Power Weak Inversion Composite MOS Transistor: Concept and Applications |
PDF
|
| Luis H.C. FERREIRA, Tales C. PIMENTA, Robson L. MORENO | 662-665 |
| High-Input and Low-Output Impedance Voltage-Mode Universal DDCC and FDCCII Filter |
PDF
|
| Hua-Pin CHEN, Wan-Shing YANG | 666-669 |
| A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters |
PDF
|
| Kicheol KIM, Youbean KIM, Incheol KIM, Hyeonuk SON, Sungho KANG | 670-672 |
Papers
| A Low-Power Instruction Issue Queue for Microprocessors |
PDF
|
| Shingo WATANABE, Akihiro CHIYONOBU, Toshinori SATO | 400-409 |
| Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems |
PDF
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| Makoto SUGIHARA, Tohru ISHIHARA, Kazuaki MURAKAMI | 410-417 |
| Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems |
PDF
|
| Hamid NOORI, Maziar GOUDARZI, Koji INOUE, Kazuaki MURAKAMI | 418-431 |
| Power-Aware Compiler Controllable Chip Multiprocessor |
PDF
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| Hiroaki SHIKANO, Jun SHIRAKO, Yasutaka WADA, Keiji KIMURA, Hironori KASAHARA | 432-439 |
| Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm |
PDF
|
| Yibo FAN, Takeshi IKENAGA, Satoshi GOTO | 440-448 |
| A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems |
PDF
|
| Qin LIU, Seiichiro HIRATSUKA, Kazunori SHIMIZU, Shinsuke USHIKI, Satoshi GOTO, Takeshi IKENAGA | 449-456 |
| A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition |
PDF
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| Yuichiro MURACHI, Yuki FUKUYAMA, Ryo YAMAMOTO, Junichi MIYAKOSHI, Hiroshi KAWAGUCHI, Hajime ISHIHARA, Masayuki MIYAMA, Yoshio MATSUDA, Masahiko YOSHIMOTO | 457-464 |
| A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer |
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| Yuichiro MURACHI, Junichi MIYAKOSHI, Masaki HAMAMOTO, Takahiro IINUMA, Tomokazu ISHIHARA, Fang YIN, Jangchung LEE, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO | 465-478 |
| Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling |
PDF
|
| Masanori HARIYAMA, Naoto YOKOYAMA, Michitaka KAMEYAMA | 479-486 |
| Automatic Synthesis of Cost Effective FFT/IFFT Cores for VLSI OFDM Systems |
PDF
|
| Nicola E. L' INSALATA, Sergio SAPONARA, Luca FANUCCI, Pierangelo TERRENI | 487-496 |
| A Reconfigurable Functional Unit with Conditional Execution for Multi-Exit Custom Instructions |
PDF
|
| Hamid NOORI, Farhad MEHDIPOUR, Koji INOUE, Kazuaki MURAKAMI | 497-508 |
| Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing |
PDF
|
| Akihiro NAKAMURA, Masahide KAWARASAKI, Kouta ISHIBASHI, Masaya YOSHIKAWA, Takeshi FUJINO | 509-516 |
| Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment |
PDF
|
| Hasitha Muthumala WAIDYASOORIYA, Weisheng CHONG, Masanori HARIYAMA, Michitaka KAMEYAMA | 517-525 |
| A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model |
PDF
|
| Shinya KAJIYAMA, Ken'ichiro SONODA, Kazuo OTSUGA, Hideaki KURATA, Kiyoshi ISHIKAWA | 526-533 |
| FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction |
PDF
|
| Shin-ichi O' UCHI, Meishoku MASAHARA, Kazuhiko ENDO, Yongxun LIU, Takashi MATSUKAWA, Kunihiro SAKAMOTO, Toshihiro SEKIGAWA, Hanpei KOIKE, Eiichi SUZUKI | 534-542 |
| A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing |
PDF
|
| Hiroki NOGUCHI, Yusuke IGUCHI, Hidehiro FUJIWARA, Shunsuke OKUMURA, Yasuhiro MORITA, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO | 543-552 |
| Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array |
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| Tadayoshi ENOMOTO, Suguru NAGAYAMA, Hiroaki SHIKANO, Yousuke HAGIWARA | 553-561 |
| Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications) |
PDF
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| Kenta YAMADA, Noriaki ODA | 562-570 |
| Redundant Vias Insertion for Performance Enhancement in 3D ICs |
PDF
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| Xu ZHANG, Xiaohong JIANG, Susumu HORIGUCHI | 571-580 |
| Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling |
PDF
|
| Kazuyasu MIZUSAWA, Naoya ONIZAWA, Takahiro HANYU | 581-588 |
| Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation |
PDF
|
| Masatomo MIURA, Takahiro HANYU | 589-594 |
| Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network |
PDF
|
| Hyunjeong PARK, Hyungsoo KIM, Jun So PAK, Changwook YOON, Kyoungchoul KOO, Joungho KIM | 595-606 |
| TM Plane Wave Reflection and Transmission from a One-Dimensional Random Slab |
PDF
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| Yasuhiko TAMURA | 607-614 |
| Design Method for a Low-Profile Dual-Shaped Reflector Antenna with an Elliptical Aperture by the Suppression of Undesired Scattering |
PDF
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| Yoshio INASAWA, Shinji KURODA, Kenji KUSAKABE, Izuru NAITO, Yoshihiko KONISHI, Shigeru MAKINO, Makio TSUCHIYA | 615-624 |
| Planar T-Shaped Monopole Antenna for WLAN/WiMAX Applications |
PDF
|
| Jhin-Fang HUANG, Shih-Huang WU | 625-630 |
| Characterization of Two-Stage Composite Right- and Left-Handed Transmission Lines |
PDF
|
| Shun NAKAGAWA, Koichi NARAHARA | 631-637 |
| Computer Simulation about Temperature Distribution of an EM-Wave Absorber Using a Coupled Analysis Method |
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|
| Shinya WATANABE, Akitoshi TANIGUCHI, Kota SAITO, Osamu HASHIMOTO, Toshifumi SAITO, Hiroshi KURIHARA | 638-646 |
| Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis |
PDF
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| Masakazu AOKI, Shin-ichi OHKAWA, Hiroo MASUDA | 647-654 |
| A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI |
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| Yusuke OHTOMO, Hiroshi KOIZUMI, Kazuyoshi NISHIMURA, Masafumi NOGAWA | 655-661 |