| Issue | Title | |
| Vol. E88-C, No. 4 April 2005 | 0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier | Details |
| Toshikazu SUZUKI, Yoshinobu YAMAGAMI, Ichiro HATANAKA, Akinori SHIBAYAMA, Hironori AKAMATSU, Hiroyuki YAMAUCHI | ||
| Vol. E88-C, No. 2 February 2005 | 1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation | Details |
| Shizunori MATSUMOTO, Hiroaki UENO, Satoshi HOSOKAWA, Toshihiko KITAMURA, Mitiko MIURA- MATTAUSCH, Hans Jurgen MATTAUSCH, Tatsuya OHGURO, Shigetaka KUMASHIRO, Tetsuya YAMAGUCHI, Kyoji YAMASHITA, Noriaki NAKAYAMA | ||
| Vol. E89-C, No. 1 January 2006 | 10 GHz Low-Noise Low-Power Monolithic Integrated VCOs in Digital CMOS Technology | Details |
| Zheng GU, Andreas THIEDE | ||
| Vol. E90-C, No. 5 May 2007 | 10-Bit Current Driver LSI for Large-Size and High-Resolution Active Matrix Organic Light Emitting Diode Displays | Details |
| Il-Hun JEONG, Oh-Kyong KWON | ||
| Vol. E90-C, No. 3 March 2007 | 11-Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic | Details |
| Sun Hong AHN, Jeong Beom KIM | ||
| Vol. E91-C, No. 7 July 2008 | 1.8 V Operation Power Amplifier IC for Bluetooth Class 1 Utilizing p+-GaAs Gate Hetero-Junction FET | Details |
| Fumio HARIMA, Yasunori BITO, Hidemasa TAKAHASHI, Naotaka IWATA | ||
| Vol. E90-C, No. 4 April 2007 | 18-GHz Clock Distribution Using a Coupled VCO Array | Details |
| Takayuki SHIBASAKI, Hirotaka TAMURA, Kouichi KANDA, Hisakatsu YAMAGUCHI, Junji OGAWA, Tadahiro KURODA | ||
| Vol. E88-C, No. 8 August 2005 | 2.4/5.2 GHz Dual Band CMOS Driver Stage with Integrated 5.2 GHz Power Amplifier | Details |
| YunSeong EO, KwangDu LEE | ||
| Vol. E89-C, No. 12 December 2006 | 2D Beam Scanning Planar Antenna Array Using Composite Right/Left-Handed Leaky Wave Antennas | Details |
| Tokio KANEDA, Atsushi SANADA, Hiroshi KUBO | ||
| Vol. E88-C, No. 8 August 2005 | 2-D Model for Calculating Current Density Distribution and Flux-Flow Resistivity of MCP BSCCO-2212 Rod during Quenching Process in Self Field | Details |
| Jian LI, Mingzhe RONG | ||
| Vol. E90-C, No. 7 July 2007 | 3.5-GHz-Band Low-Bias-Current Operation 0/20-dB Step Linearized Attenuators Using GaAs-HBT Compatible, AC-Coupled, Stack Type Base-Collector Diode Switch Topology | Details |
| Kazuya YAMAMOTO, Miyo MIYASHITA, Nobuyuki OGAWA, Takeshi MIURA, Teruyuki SHIMURA | ||
| Vol. E90-C, No. 12 December 2007 | 360-µW/1 mW Complementary Cross-Coupled Differential Colpitts LC-VCO/QVCO in 0.25-µm CMOS | Details |
| Jong-Phil HONG, Seok-Ju YUN, Sang-Gug LEE | ||
| Vol. E89-C, No. 10 October 2006 | 3D Error Diffusion Method Based on Edge Detection for Flat Panel Display | Details |
| Zujun LIU, Chunliang LIU, Shengli WU | ||
| Vol. E91-C, No. 8 August 2008 | 3-D Finite Element Analysis of Dynamic Characteristics of Twin-Type Relay Interfered by Uniform Constant Magnetic Field | Details |
| Guofu ZHAI, Wenying YANG, Xue ZHOU | ||
| Vol. E89-C, No. 5 May 2006 | 3D Inspection on Wafer Solder Bumps Using Binary Grating Projection in Integrated Circuit Manufacturing | Details |
| Shu YUAN, Dongping TIAN, Yanxing ZENG | ||
| Vol. E91-C, No. 11 November 2008 | 4.8 GHz CMOS Frequency Multiplier Using Subharmonic Pulse-Injection Locking for Spurious Suppression | Details |
| Kyoya TAKANO, Mizuki MOTOYOSHI, Minoru FUJISHIMA | ||
| Vol. E90-C, No. 11 November 2007 | 4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words | Details |
| Koh JOHGUCHI, Hans Jurgen MATTAUSCH, Tetsushi KOIDE, Tetsuo HIRONAKA | ||
| Vol. E91-C, No. 6 June 2008 | 55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers | Details |
| Tomohiko ITO, Daisuke KUROSE, Takeshi UENO, Takafumi YAMAJI, Tetsuro ITAKURA | ||
| Vol. E89-C, No. 12 December 2006 | 60 GHz Bandpass Filter Using NRD Guide E-Plane Resonators | Details |
| Takashi SHIMIZU, Tsukasa YONEYAMA | ||
| Vol. E88-C, No. 6 June 2005 | 64-Bit High-Performance Power-Aware Conditional Carry Adder Design | Details |
| Kuo-Hsing CHENG, Shun-Wen CHENG | ||
| Vol. E91-C, No. 3 March 2008 | 6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator | Details |
| Yun-Jeong KIM, Jong-Ho LEE, Ja-Hyun KOO, Kwang-Hyun BAEK, Suki KIM | ||
| Vol. E89-C, No. 7 July 2006 | 763-nm Laser Light Source for Oxygen Monitoring Using Second Harmonic Generation in Direct-Bonded Quasi-Phase-Matched LiNbO3 Ridge Waveguide | Details |
| Osamu TADANAGA, Masaki ASOBE, Yoshiki NISHIDA, Hiroshi MIYAZAWA, Kaoru YOSHINO, Hiroyuki SUZUKI | ||
| Vol. E91-C, No. 12 December 2008 | In-situ Measurement of Photoelectron Spectroscopy in Air of Polypyrrole during Electrochemical Undoping | Details |
| Kazuya TADA, Yoshinori MIYOSHI, Mitsuyoshi ONODA | ||
| Vol. E88-C, No. 5 May 2005 | RFCV Test Structure Design for a Selected Frequency Range | Details |
| Wutthinan JEAMSAKSIRI, Abdelkarim MERCHA, Javier RAMOS, Stefaan DECOUTERE, Florence CUBAYNES | ||
| Vol. E88-C, No. 8 August 2005 | V-I Characteristics of Short Gap Arc in Air at C, Ag, Cu, Pd, and W Electrodes--Measurement and Formulation for Practical Use-- | Details |
| Keiichi SUHARA | ||
| Vol. E90-C, No. 9 September 2007 | Vdd Gate Biasing RF CMOS Amplifier Design Technique Based on the Effect of Carrier Velocity Saturation | Details |
| Noboru ISHIHARA | ||
| Vol. E89-C, No. 10 October 2006 | A 0.18 µm CMOS 3.125-Gb/s Digitally Controlled Adaptive Line Equalizer with Feed-Forward Swing Control for Backplane Serial Link | Details |
| Ki-Hyuk LEE, Jae-Wook LEE, Woo-Young CHOI | ||
| Vol. E90-C, No. 9 September 2007 | A 0.7 V 3-5 GHz CMOS Low Noise Amplifier for Ultra-Wideband Applications | Details |
| Chih-Lung HSIAO, Ro-Min WENG, Wei-Chi LEE | ||
| Vol. E91-C, No. 9 September 2008 | A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture | Details |
| Hsin-Hung OU, Bin-Da LIU, Soon-Jyh CHANG | ||
| Vol. E91-C, No. 1 January 2008 | A 0.8-V Syllabic-Companding Log Domain Filter with 78-dB Dynamic Range in 0.35-µm CMOS | Details |
| Ippei AKITA, Kazuyuki WADA, Yoshiaki TADOKORO | ||
| Vol. E89-C, No. 6 June 2006 | A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique | Details |
| Takeshi YOSHIDA, Yoshihiro MASUI, Takayuki MASHIMO, Mamoru SASAKI, Atsushi IWATA | ||
| Vol. E89-C, No. 3 March 2006 | A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology | Details |
| Chi-Nan CHUANG, Shen-Iuan LIU | ||
| Vol. E90-C, No. 10 October 2007 | A 10 b 200 MS/s 1.8 mm2 83 mW 0.13 µm CMOS ADC Based on Highly Linear Integrated Capacitors | Details |
| Young-Ju KIM, Young-Jae CHO, Doo-Hwan SA, Seung-Hoon LEE | ||
| Vol. E90-C, No. 10 October 2007 | A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications | Details |
| Hidehiro TOYODA, Shinji NISHIMURA, Michitaka OKUNO, Matsuaki TERADA | ||
| Vol. E89-C, No. 5 May 2006 | A 10b 100 MS/s 1.4 mm2 56 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors | Details |
| Byoung-Han MIN, Young-Jae CHO, Hee-Sung CHAE, Hee-Won PARK, Seung-Hoon LEE | ||
| Vol. E91-C, No. 6 June 2008 | A 10-Gb/s Burst-Mode Clock-and-Data Recovery IC with Frequency-Adjusting Dual Gated VCOs | Details |
| Yusuke OHTOMO, Masafumi NOGAWA, Kazuyoshi NISHIMURA, Shunji KIMURA, Tomoaki YOSHIDA, Tomoaki KAWAMURA, Minoru TOGASHI, Kiyomi KUMOZAKI | ||
| Vol. E91-C, No. 4 April 2008 | A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing | Details |
| Hiroki NOGUCHI, Yusuke IGUCHI, Hidehiro FUJIWARA, Shunsuke OKUMURA, Yasuhiro MORITA, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO | ||
| Vol. E91-C, No. 2 February 2008 | A 12 b 200 kS/s 0.52 mA 0.47 mm2 Algorithmic A/D Converter for MEMS Applications | Details |
| Young-Ju KIM, Hee-Cheol CHOI, Seung-Hoon LEE, Dongil "Dan" CHO | ||
| Vol. E89-C, No. 3 March 2006 | A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology | Details |
| Daisuke MIZOGUCHI, Noriyuki MIURA, Takayasu SAKURAI, Tadahiro KURODA | ||
| Vol. E90-C, No. 1 January 2007 | A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation | Details |
| Ching-Yuan YANG, Jung-Mao LIN | ||
| Vol. E90-C, No. 1 January 2007 | A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution | Details |
| Chang-Kyung SEONG, Seung-Woo LEE, Woo-Young CHOI | ||
| Vol. E90-C, No. 11 November 2007 | A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology | Details |
| Hideaki KURATA, Satoshi NODA, Yoshitaka SASAGO, Kazuo OTSUGA, Tsuyoshi ARIGANE, Tetsufumi KAWAMURA, Takashi KOBAYASHI, Hitoshi KUME, Kazuki HOMMA, Teruhiko ITO, Yoshinori SAKAMOTO, Masahiro SHIMIZU, Yoshinori IKEDA, Osamu TSUCHIYA, Kazunori FURUSAWA | ||
| Vol. E89-C, No. 10 October 2006 | A 130-nm CMOS 95-mm2 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput | Details |
| Hideaki KURATA, Shunichi SAEKI, Takashi KOBAYASHI, Yoshitaka SASAGO, Tsuyoshi ARIGANE, Keiichi YOSHIDA, Yoshinori TAKASE, Takayuki YOSHITAKE, Osamu TSUCHIYA, Yoshinori IKEDA, Shunichi NARUMI, Michitaro KANAMITSU, Kazuto IZAWA, Kazunori FURUSAWA | ||
| Vol. E88-C, No. 4 April 2005 | A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory | Details |
| Shoichi MASUI, Toshiyuki TERAMOTO | ||
| Vol. E90-C, No. 4 April 2007 | A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses | Details |
| Hiroyuki YAMAUCHI, Toshikazu SUZUKI, Yoshinobu YAMAGAMI | ||
| Vol. E88-C, No. 4 April 2005 | A 1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks | Details |
| Jun TERADA, Yasuyuki MATSUYA, Shin'ichiro MUTOH, Yuichi KADO | ||
| Vol. E88-C, No. 4 April 2005 | A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters | Details |
| Toru TANZAWA, Kenichi AGAWA, Hiroyuki SHIBAYAMA, Ryota TERAUCHI, Katsumi HISANO, Hiroki ISHIKURO, Shouhei KOUSAI, Hiroyuki KOBAYASHI, Hideaki MAJIMA, Toru TAKAYAMA, Masayuki KOIZUMI, Fumitoshi HATORI | ||
| Vol. E88-C, No. 6 June 2005 | A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation | Details |
| Hideyuki NOSAKA, Makoto NAKAMURA, Kimikazu SANO, Minoru IDA, Kenji KURISHIMA, Tsugumichi SHIBATA, Masami TOKUMITSU, Masahiro MURAGUCHI | ||
| Vol. E88-C, No. 6 June 2005 | A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique | Details |
| Mitsuru SHIOZAKI, Toru MUKAI, Masahiro ONO, Mamoru SASAKI, Atsushi IWATA | ||
| Vol. E91-C, No. 1 January 2008 | A 2-GHz Low-Power Down-Conversion Mixer in 0.18-µm CMOS Technology | Details |
| Jun-Da CHEN, Zhi-Ming LIN, Jeen-Sheen ROW | ||
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