A 0.3-V Operating,  V  th -Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

A 0.3-V Operating, V_th-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Kentaro KAWAKAMI, Junichi MIYAKOSHI, Shinji MIKAMI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO

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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond

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A 0.3-V Operating, V_th-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond