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Table of Contents
Foreword
| FOREWORD |
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| Hidetoshi ONODERA | 3377-3377 |
Letters
| Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation |
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| Toshiki KANAMOTO, Shigekiyo AKUTSU, Tamiyo NAKABAYASHI, Takahiro ICHINOMIYA, Koutaro HACHIYA, Atsushi KUROKAWA, Hiroshi ISHIKAWA, Sakae MUROMOTO, Hiroyuki KOBAYASHI, Masanori HASHIMOTO | 3666-3670 |
| Steady-State Properties of a CORDIC-Based Adaptive ARMA Lattice Filter |
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| Shin'ichi SHIRAISHI, Miki HASEYAMA, Hideo KITAJIMA | 3724-3729 |
| Grounded-Capacitor First-Order Filter Using Minimum Components |
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| Hua-Pin CHEN, Kuo-Hsiung WU | 3730-3731 |
| New Digital Fingerprint Code Construction Scheme Using Group-Divisible Design |
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| InKoo KANG, Kishore SINHA, Heung-Kyu LEE | 3732-3735 |
| First Derivatives Estimation of Nonlinear Parameters in Hybrid System |
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| Jung-Wook PARK, Byoung-Kon CHOI, Kyung-Bin SONG | 3736-3738 |
Papers
| Memory Size Computation for Real-Time Multimedia Applications Based on Polyhedral Decomposition |
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| Hongwei ZHU, Ilie I. LUICAN, Florin BALASA | 3378-3386 |
| Synchronization Verification in System-Level Design with ILP Solvers |
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| Thanyapat SAKUNKONCHAK, Satoshi KOMATSU, Masahiro FUJITA | 3387-3396 |
| The AMS Extension to System Level Design Language--SpecC |
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| Yu LIU, Satoshi KOMATSU, Masahiro FUJITA | 3397-3407 |
| Unified Representation for Speculative Scheduling: Generalized Condition Vector |
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| Kazutoshi WAKABAYASHI | 3408-3415 |
| An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs |
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| Mitsuru TOMONO, Masaki NAKANISHI, Shigeru YAMASHITA, Kazuo NAKAJIMA, Katsumasa WATANABE | 3416-3426 |
| Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique |
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| Nobuhiro DOI, Takashi HORIYAMA, Masaki NAKANISHI, Shinji KIMURA | 3427-3434 |
| Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits |
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| Bakhtiar Affendi ROSDI, Atsushi TAKAHASHI | 3435-3442 |
| Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries |
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| Debatosh DEBNATH, Tsutomu SASAO | 3443-3450 |
| Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification |
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| Xingwen XU, Shinji KIMURA, Kazunari HORIKAWA, Takehiko TSUCHIYA | 3451-3457 |
| Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs |
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| Yuichi NAKAMURA, Takeshi YOSHIMURA | 3458-3463 |
| Fast FPGA-Emulation-Based Simulation Environment for Custom Processors |
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| Yuichi NAKAMURA, Kouhei HOSOKAWA | 3464-3470 |
| A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator |
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| Hiroki NAKAHARA, Tsutomu SASAO, Munehiro MATSUURA | 3471-3481 |
| Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits |
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| Naoaki OHKUBO, Kimiyoshi USAMI | 3482-3490 |
| On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature |
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| Takashi SATO, Junji ICHIMIYA, Nobuto ONO, Masanori HASHIMOTO | 3491-3499 |
| Formal Design of Arithmetic Circuits Based on Arithmetic Description Language |
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| Naofumi HOMMA, Yuki WATANABE, Takafumi AOKI, Tatsuo HIGUCHI | 3500-3509 |
| Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method |
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| Shinobu NAGAYAMA, Tsutomu SASAO, Jon T. BUTLER | 3510-3518 |
| Design Method of High Performance and Low Power Functional Units Considering Delay Variations |
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| Kouichi WATANABE, Masashi IMAI, Masaaki KONDO, Hiroshi NAKAMURA, Takashi NANYA | 3519-3528 |
| A Structural Approach for Transistor Circuit Synthesis |
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| Hiroaki YOSHIDA, Makoto IKEDA, Kunihiro ASADA | 3529-3537 |
| A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays |
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| Shingo TAKAHASHI, Shuji TSUKIYAMA, Masanori HASHIMOTO, Isao SHIRAKAWA | 3538-3545 |
| LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil |
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| Taisuke KAZAMA, Makoto IKEDA, Kunihiro ASADA | 3546-3550 |
| Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages |
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| Yoichi TOMIOKA, Atsushi TAKAHASHI | 3551-3559 |
| Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design |
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| Toshiki KANAMOTO, Tatsuhiko IKEDA, Akira TSUCHIYA, Hidetoshi ONODERA, Masanori HASHIMOTO | 3560-3568 |
| Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's |
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| Danardono Dwi ANTONO, Kenichi INAGAKI, Hiroshi KAWAGUCHI, Takayasu SAKURAI | 3569-3578 |
| Statistical Modeling of a Via Distribution for Yield Estimation |
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| Takumi UEZONO, Kenichi OKADA, Kazuya MASU | 3579-3584 |
| Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line |
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| Akira TSUCHIYA, Masanori HASHIMOTO, Hidetoshi ONODERA | 3585-3593 |
| A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization |
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| Yang SONG, Zhenyu LIU, Takeshi IKENAGA, Satoshi GOTO | 3594-3601 |
| Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule |
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| Kazunori SHIMIZU, Tatsuyuki ISHIKAWA, Nozomu TOGAWA, Takeshi IKENAGA, Satoshi GOTO | 3602-3612 |
| VLSI Implementation of a Modified Efficient SPIHT Encoder |
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| Win-Bin HUANG, Alvin W. Y. SU, Yau-Hwang KUO | 3613-3622 |
| A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture |
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| Junichi MIYAKOSHI, Yuichiro MURACHI, Tetsuro MATSUNO, Masaki HAMAMOTO, Takahiro IINUMA, Tomokazu ISHIHARA, Hiroshi KAWAGUCHI, Masayuki MIYAMA, Masahiko YOSHIMOTO | 3623-3633 |
| A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond |
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| Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Kentaro KAWAKAMI, Junichi MIYAKOSHI, Shinji MIKAMI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO | 3634-3641 |
| A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline |
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| Kentaro KAWAKAMI, Jun TAKEMURA, Mitsuhiko KURODA, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO | 3642-3651 |
| Fault Tolerant Dynamic Reconfigurable Device Based on EDAC with Rollback |
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| Kentaro NAKAHARA, Shin'ichi KOUYAMA, Tomonori IZUMI, Hiroyuki OCHI, Yukihiro NAKAMURA | 3652-3658 |
| A Parallel-In Folding Technique for High-Order FIR Filter Implementation |
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| Lan-Rong DUNG, Hsueh-Chih YANG | 3659-3665 |
| Target-Oriented Acoustic Radiation Generation Technique for Sound Field Control |
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| Yuan WEN, Jun YANG, Woon-Seng GAN | 3671-3677 |
| Estimation of Color Images by Box Splines from Their Observation through Honeycomb Color Filter |
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| Tomoko YOKOKAWA, Masaru KAMADA, Yasuhiro OHTAKI, Tatsuhiro YONEKURA | 3678-3684 |
| Miller Capacitor with Wide Input Range and Its Application to PLL Loop Filter |
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| Masahiro YOSHIOKA, Nobuo FUJII | 3685-3692 |
| Necessary and Sufficient Conditions for One-Dimensional Discrete-Time Autonomous Binary Cellular Neural Networks to Be Stable |
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| Tetsuo NISHI, Norikazu TAKAHASHI, Hajime HARA | 3693-3698 |
| On the Expected Prediction Error of Orthogonal Regression with Variable Components |
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| Katsuyuki HAGIWARA, Hiroshi ISHITANI | 3699-3709 |
| Properties of a Word-Valued Source with a Non-prefix-free Word Set |
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| Takashi ISHIDA, Masayuki GOTO, Toshiyasu MATSUSHIMA, Shigeichi HIRASAWA | 3710-3723 |