Table of Contents
Foreword
| FOREWORD |
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| Yusuke MATSUNAGA | 705-706 |
Letters
| Computing Transformation Matrix for Bilinear S-Z Transformation |
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| Younseok CHOO | 872-874 |
| Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis |
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| Eui-Young CHUNG, Hyuk-Jun LEE, Sung Woo CHUNG | 875-878 |
| MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications |
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| Terng-Ren HSU, Chien-Ching LIN, Terng-Yin HSU, Chen-Yi LEE | 879-884 |
Papers
| Control-Invariance of Sampled-Data Hybrid Systems with Clocked Events and Jitters |
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| Yoshiyuki TSUCHIE, Toshimitsu USHIO | 707-714 |
| Design of a Neural Network Chip for the Burst ID Model with Ability of Burst Firing |
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| Shinya SUENAGA, Yoshihiro HAYAKAWA, Koji NAKAJIMA | 715-723 |
| Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect |
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| Yasuhiro OGASAHARA, Masanori HASHIMOTO, Takao ONOYE | 724-731 |
| Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System |
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| Zhangcai HUANG, Yasuaki INOUE, Hong YU, Jun PAN, Yun YANG, Quan ZHANG, Shuai FANG | 732-740 |
| Fast Methods to Estimate Clock Jitter due to Power Supply Noise |
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| Koutaro HACHIYA, Takayuki OHSHIMA, Hidenari NAKASHIMA, Masaaki SODA, Satoshi GOTO | 741-747 |
| A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect |
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| Jun PAN, Yasuaki INOUE, Zheng LIANG, Zhangcai HUANG, Weilun HUANG | 748-755 |
| Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation |
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| Ming SHAO, Zhenyu LIU, Satoshi GOTO, Takeshi IKENAGA | 756-763 |
| Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation |
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| Yang SONG, Zhenyu LIU, Takeshi IKENAGA, Satoshi GOTO | 764-770 |
| Lossless Data Hiding in the Spatial Domain for High Quality Images |
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| Hong Lin JIN, Masaaki FUJIYOSHI, Hitoshi KIYA | 771-777 |
| Global Noise Estimation Based on Tensor Product Expansion with Absolute Error |
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| Akitoshi ITAI, Hiroshi YASUKAWA, Ichi TAKUMI, Masayasu HATA | 778-783 |
| A Simulation Platform for Designing Cell-Array-Based Self-Reconfigurable Architecture |
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| Shin'ichi KOUYAMA, Tomonori IZUMI, Hiroyuki OCHI, Yukihiro NAKAMURA | 784-791 |
| A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units |
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| Tsuyoshi SADAKATA, Yusuke MATSUNAGA | 792-799 |
| Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization |
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| Yukihide KOHIRA, Atsushi TAKAHASHI | 800-807 |
| Proposal of Metrics for SSTA Accuracy Evaluation |
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| Hiroyuki KOBAYASHI, Nobuto ONO, Takashi SATO, Jiro IWAI, Hidenari NAKASHIMA, Takaaki OKUMURA, Masanori HASHIMOTO | 808-814 |
| A Fast Characterizing Method for Large Embedded Memory Modules on SoC |
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| Masahiko OMURA, Toshiki KANAMOTO, Michiko TSUKAMOTO, Mitsutoshi SHIROTA, Takashi NAKAJIMA, Masayuki TERAI | 815-822 |
| A Surjective Mapping from Permutations to Room-to-Room Floorplans |
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| Ryo FUJIMAKI, Toshihiko TAKAHASHI | 823-828 |
| WF-Net Based Modeling and Soundness Verification of Interworkflows |
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| Shingo YAMAGUCHI, Hajime MATSUO, Qi-Wei GE, Minoru TANAKA | 829-835 |
| A Tableau Construction Approach to Control Synthesis of FSMs Using Simulation Relations |
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| Yoshisato SAKAI | 836-846 |
| Performance Comparison of Algorithms for the Dynamic Shortest Path Problem |
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| Satoshi TAOKA, Daisuke TAKAFUJI, Takashi IGUCHI, Toshimasa WATANABE | 847-856 |
| Autocorrelation and Linear Complexity of the New Generalized Cyclotomic Sequences |
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| Tongjiang YAN, Rong SUN, Guozhen XIAO | 857-864 |
| Competing Behavior of Two Kinds of Self-Organizing Maps and Its Application to Clustering |
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| Haruna MATSUSHITA, Yoshifumi NISHIO | 865-871 |